1. Technical Field
The present disclosure generally relates to a strained channel FinFET device and, in particular, a high-germanium concentration strained channel FinFET device built on a substrate having a buried oxide layer.
2. Description of the Related Art
Advanced integrated circuits typically feature strained channel devices, silicon-on-insulator substrates, FinFET structures, or combinations thereof, in order to continue scaling transistor gate lengths below 20 nm. Such technologies allow the channel length of the transistor to shrink while minimizing detrimental consequences such as current leakage and other short channel effects.
A FinFET is an electronic switching device in which a conventional planar semiconducting channel is replaced by a semiconducting fin that extends outward from the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence the current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance and reduced current leakage.
Incorporating strain into the channel of a semiconductor device alters the crystal lattice so as to increase charge carrier mobility in the channel. With greater carrier mobility, the device becomes a more responsive switch. Introducing a tensile strain into an NFET transistor stretches the crystal lattice, thereby increasing electron mobility in the channel, and resulting in a faster switching response to changes in voltage applied to the transistor gate. Likewise, introducing a compressive strain into a PFET transistor tends to increase hole mobility in the channel, also resulting in a faster switching response.
There are many ways to introduce strain into the channel region of a silicon transistor. Such techniques typically entail incorporating into the device epitaxial layers of one or more materials having crystal lattice dimensions or geometries that differ slightly from those of the silicon substrate. The epitaxial layers can be made of doped silicon or silicon germanium (SiGe), for example. Epitaxial layers can be incorporated into source and drain regions, into the transistor gate that is used to modulate current flow in the channel, or into the channel itself, which is a portion of the fin. In a FinFET, SiGe can be introduced by growing epitaxial sidewall extensions of the silicon fin to form a cladding.
Alternatively, strain can be induced in the fin from below the device by using various types of silicon-on-insulator (SOI) substrates. An SOI substrate features a buried insulator, typically a buried oxide layer (BOX) underneath the active area. SOI FinFET devices have been disclosed in patent applications assigned to the present assignee, for example, U.S. patent application Ser. No. 14/231,466, entitled “SOI FinFET Transistor with Strained Channel,” which is hereby incorporated by reference in its entirety.